17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator.
Younghyun LimJuyeop KimYongwoo JoJooeun BangSeyeon YooHangi ParkHeein YoonJaehyouk ChoiPublished in: ISSCC (2020)
Keyphrases
- low power
- high speed
- clock frequency
- power consumption
- cmos technology
- single chip
- high power
- low cost
- digital signal processing
- wireless transmission
- real time
- vlsi architecture
- gate array
- power saving
- logic circuits
- low power consumption
- mixed signal
- nm technology
- image processing
- delay insensitive
- image sensor
- power reduction
- power dissipation
- low frequency
- ultra low power