Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.
Michael Bedford TaylorWalter LeeSaman P. AmarasingheAnant AgarwalPublished in: HPCA (2003)
Keyphrases
- high speed
- high bandwidth
- software architecture
- low cost
- analog vlsi
- vlsi implementation
- real time
- network structure
- inductive logic programming
- management system
- future internet
- vector valued
- social networks
- polynomial neural networks
- functional units
- power dissipation
- relational learning
- data flow
- complex networks
- input output
- high density
- cmos technology
- design methodology
- level parallelism
- end to end