A Case Study of Formal Verification for Multi-level Pipeline Logic Circuit by using Mizar Proof Checker.
Katsumi WasakiKen-ichi AraiPublished in: FCS (2007)
Keyphrases
- formal verification
- model checker
- bounded model checking
- model checking
- proof theory
- digital circuits
- delay insensitive
- logic circuits
- asynchronous circuits
- logic synthesis
- natural deduction
- linear logic
- symbolic model checking
- proof search
- automated verification
- automated reasoning
- chip design
- high speed
- proof theoretic
- temporal logic
- theorem proving
- theorem prover
- logical rules
- modal logic
- computer assisted
- higher order logic
- sequent calculi
- case study
- sequent calculus
- cut elimination
- linear temporal logic
- set theory
- micron cmos
- automated theorem proving
- circuit design
- multi valued
- classical logic
- inference rules
- logical framework
- logic programming
- complete axiomatization
- analog circuits