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Designing Chip-Level Nanophotonic Interconnection Networks.

Christopher BattenAjay JoshiVladimir StojanovicKrste Asanovic
Published in: IEEE J. Emerg. Sel. Topics Circuits Syst. (2012)
Keyphrases
  • interconnection networks
  • high speed
  • low cost
  • fault tolerant
  • multistage
  • routing algorithm
  • wireless sensor networks
  • network on chip
  • image segmentation
  • data processing