A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.
Yutaka YoshidaTatsuya KameiKiyoshi HayaseShinichi ShibaharaOsamu NishiiToshihiro HattoriAtsushi HasegawaMasashi TakadaNaohiko IrieKunio UchiyamaToshihiko OdakaKiwamu TakadaKeiji KimuraHironori KasaharaPublished in: ISSCC (2007)
Keyphrases
- low power consumption
- power consumption
- clock frequency
- processor core
- field programmable gate array
- low power
- parallel computing
- massively parallel
- operating system
- low cost
- ibm zenterprise
- data center
- real time
- hardware implementation
- cmos technology
- parallel algorithm
- shared memory
- computing systems
- embedded systems
- parallel processing
- special purpose
- high performance computing
- input output