Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications.
Daniel MorrisonDennis DelicMehmet Rasit YuceJean-Michel RedoutePublished in: IEEE Trans. Very Large Scale Integr. Syst. (2019)
Keyphrases
- shift register
- multistage
- high speed
- focal plane
- random number generator
- low power
- production system
- single stage
- stochastic programming
- dynamic programming
- hardware implementation
- lot sizing
- cmos technology
- random access memory
- stochastic optimization
- optimal policy
- real time
- image sensor
- delay insensitive
- multistage stochastic
- finite horizon
- capacity expansion
- low cost
- lot streaming
- nm technology