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High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic.
Avadhoot Khairnar
Bhavuk Chauhan
Geetanjali Sharma
Amit M. Joshi
Published in:
J. Circuits Syst. Comput. (2022)
Keyphrases
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bit parallel
hybrid learning
logic circuits
case study
building blocks
power consumption
propositional logic
design methodology
power dissipation
chip design
neural network
user interface
low cost
design process
circuit design