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Circuit Techniques to Enhance Linearity and Intrinsic Gain to Realize a 1.2 V, 200 MHz, +10.3 dBm IIP3 and 7th-Order LPF in a 65 nm CMOS.

Yasuhiro SugimotoKazuma Sakatoh
Published in: IEICE Trans. Electron. (2013)
Keyphrases
  • high speed
  • cmos technology
  • analog vlsi
  • low power
  • circuit design
  • real time
  • data sets
  • nm technology