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A study of row-based area-array I/O design planning in concurrent chip-package design flow.

Ren-Jie LeeHung-Ming Chen
Published in: ACM Trans. Design Autom. Electr. Syst. (2013)
Keyphrases
  • building blocks
  • computer aided
  • programmable logic
  • neural network
  • empirical studies
  • physical design