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A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology.

Woo-Rham BaeDeog-Kyoon JeongByoung-Joo Yoo
Published in: DDECS (2014)
Keyphrases
  • multi channel
  • cmos technology
  • mixed signal
  • low power
  • power consumption
  • parallel processing
  • power dissipation
  • low cost
  • single channel
  • low voltage
  • phase locked loop
  • high speed
  • signal processing
  • digital circuits