Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes.
Robert PolsterYvain ThonnartGuillaume WaltenerJose-Luis Gonzalez JimenezEric CassanPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2016)
Keyphrases
- silicon on insulator
- metal oxide semiconductor
- cmos technology
- low cost
- low power
- integrated circuit
- nm technology
- low voltage
- power consumption
- parallel processing
- ibm power processor
- high speed
- optimization problems
- strongly connected
- graph structure
- directed graph
- evolutionary algorithm
- physical characteristics
- case study