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Design of a power-efficient ARM processor with a timing-error detection and correction mechanism.

Sao-Jie ChenGrace LiuHsin-Ping YangCheng-Hao LuoWen-Mei W. Hwu
Published in: SoCC (2016)
Keyphrases
  • error detection and correction
  • single chip
  • chip design
  • ibm power processor
  • data mining
  • functional verification