A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS.
Bharath RaghavanDelong CuiUllas SinghHassan MaarefiDeyi PiAnand VasaniZhi Chao HuangBurak ÇatliAfshin MomtazJun CaoPublished in: IEEE J. Solid State Circuits (2013)
Keyphrases
- power supply
- high speed
- silicon on insulator
- cmos technology
- power consumption
- user interface
- communication systems
- low cost
- low power
- nm technology
- multiple input multiple output
- intelligent control
- circuit design
- direct manipulation
- analog vlsi
- channel state information
- interface design
- neural network
- video sequences
- channel estimation
- delay insensitive
- received signal
- amplitude modulation
- real time