Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random Number Generation.
Arjun Singh ChauhanVineet SahulaA. S. MandalAbhigyan DuttaPublished in: VLSI Design (2020)
Keyphrases
- random number
- random number generator
- random numbers
- pseudorandom
- random number generators
- real time image processing
- reverse engineering
- real time
- hardware implementation
- high speed
- field programmable gate array
- neural network
- pseudo random number generators
- malware detection
- privacy preserving
- low cost
- software engineering
- wireless sensor networks
- database systems
- verilog hdl