Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC.
Bruce QuerbachRahul KhannaSudeep PuligundlaDavid BlankenbecklerJoseph CropPatrick Yin ChiangPublished in: IEEE Des. Test (2016)
Keyphrases
- multithreading
- power consumption
- nm technology
- optimization algorithm
- low power
- optimization problems
- memory subsystem
- computational power
- power management
- memory management
- detection method
- memory requirements
- object detectors
- detection algorithm
- object detection
- cmos technology
- power dissipation
- inference engine
- memory access
- hardware and software
- associative memory
- software architecture
- training examples
- real time
- power losses
- training process
- main memory
- optimization method
- anomaly detection
- database management systems
- neural network