Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.
Minho WonHassan AlbalawiXin LiDonald E. ThomasPublished in: EMBC (2014)
Keyphrases
- hardware implementation
- low power
- discrete cosine transform
- brain computer interface
- signal processing
- filter bank
- power consumption
- high speed
- low cost
- dct coefficients
- image compression
- motor imagery
- transform domain
- low density parity check
- single chip
- image processing algorithms
- blocking artifacts
- image processing
- jpeg images
- high resolution
- pattern recognition
- dct domain
- efficient implementation
- decoding algorithm
- image blocks
- compressed images
- field programmable gate array
- image coding
- coded images
- subband
- image sensor
- wavelet transform
- multiresolution
- frequency domain