Optimization of power dissipation and skew sensitivity in clock buffer synthesis.

Jae W. Chung De-Yu Kao Chung-Kuan Cheng Ting-Ting Y. Lin

Published in: ISLPD (1995)

Keyphrases

power consumption
power dissipation
low power
high speed
analog circuits
logic circuits
power reduction
machine learning
cmos technology
digital signal processing
short circuit