Design of analog subthreshold Encoded Neural Network circuit in sub-100nm CMOS.
Benoit LarrasCyril LahuecFabrice SeguinMatthieu ArzelPublished in: IJCNN (2015)
Keyphrases
- circuit design
- neural network
- analog circuits
- analog vlsi
- cmos technology
- digital circuits
- mixed signal
- metal oxide semiconductor
- low voltage
- design process
- high speed
- vlsi architecture
- power dissipation
- chip design
- low power
- power consumption
- real time
- electronic circuits
- low cost
- artificial neural networks
- case study
- nm technology