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A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays.
Vasutan Tunbunheng
Hideharu Amano
Published in:
IEICE Trans. Inf. Syst. (2008)
Keyphrases
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graph representation
graph model
level parallelism
industry standard
programming language
high speed
instruction scheduling
general purpose
parallel processing
computer architecture
distributed memory
adjacency matrix
graphical models
multi core processors
instruction set