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Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS.

Enrico MammeiFabrizio LoiFrancesco RadiceAngelo DatiMelchiorre BruccoleriMatteo BassiAndrea Mazzanti
Published in: IEEE J. Solid State Circuits (2014)
Keyphrases
  • high speed
  • power consumption
  • data analysis
  • linear programming
  • design process
  • power reduction
  • state space
  • markov chain
  • linear program
  • single chip
  • filter design
  • power dissipation