A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs.
Linhuai TangZhihong HuangGang CaiYong ZhengJiamin ChenPublished in: Algorithms (2021)
Keyphrases
- binary tree
- quadtree
- tree representation
- high speed
- power reduction
- hierarchical structure
- data structure
- predictive coding
- analog circuits
- hardware implementation
- multiclass svm
- circuit design
- image retrieval
- electronic circuits
- similarity measure
- feature selection
- databases
- field programmable gate array
- power consumption
- hardware design
- digital circuits
- shortest path
- low cost