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A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder.
Fujun Bai
Song Wang
Xuerong Jia
Yi-Xin Guo
Bing Yu
Hang Wang
Cong Lai
Qiwei Ren
Hongbin Sun
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2023)
Keyphrases
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dynamic reconfiguration
low cost
application specific
software architecture
software systems
quality of service
response time
general purpose
main memory
dynamic behavior
high density
low power
low complexity
real time
source code
high speed
low voltage
low power consumption