A High-Speed Asynchronous Decompression Circuit for Embedded Processors.

Martin Benes Andrew Wolfe Steven M. Nowick

Published in: ARVLSI (1997)

Keyphrases

high speed
embedded processors
single chip
low power
shift register
delay insensitive
parallel implementation
data compression
real time
compression ratio
hardware and software
image compression
compression algorithm
compression scheme
frame rate
multiresolution
asynchronous circuits
high quality