A 0.18µm CMOS 10Gb/s 1: 4 DEMUX using replica-bias circuits for optical receiver.
Ju-Pyo HongKyung-Soo HaLee-Sup KimPublished in: ISCAS (2006)
Keyphrases
- high speed
- focal plane
- analog vlsi
- delay insensitive
- circuit design
- infrared
- vlsi circuits
- low power
- imaging systems
- cmos technology
- load balancing
- power dissipation
- floating gate
- chip design
- image sensor
- real time
- asynchronous circuits
- peer to peer
- fiber optic
- fault tolerance
- charge coupled device
- low variance
- mixed signal
- random access memory