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A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend.

Lei LuoKaihui LinLong ChengLiren ZhouFan YeJunyan Ren
Published in: ESSCIRC (2009)
Keyphrases
  • integer arithmetic
  • shift register
  • back end
  • random sampling
  • sampling strategy
  • multi view
  • sample size
  • markov chain monte carlo
  • doa estimation