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High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA.

Panu SjovallJanne VirtanenJarno VanneTimo D. Hämäläinen
Published in: DSD (2015)
Keyphrases
  • high level synthesis
  • low complexity
  • user interface
  • low cost
  • embedded systems
  • hardware design
  • parallel architecture
  • computer aided
  • video codec
  • computer vision
  • case study
  • low power
  • intra coding
  • power reduction