High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA.

Panu Sjovall Janne Virtanen Jarno Vanne Timo D. Hämäläinen

Published in: DSD (2015)

Keyphrases

high level synthesis
low complexity
user interface
low cost
embedded systems
hardware design
parallel architecture
computer aided
video codec
computer vision
case study
low power
intra coding
power reduction