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Post-layout verification of the WE DSP32 digital signal processor.
Laurence E. Bays
Chin-Fu Chen
Evelyn M. Fields
Renato N. Gadenz
W. Patrick Hays
Howard S. Moscovitz
Thomas G. Szymanski
Published in:
IEEE Des. Test (1989)
Keyphrases
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digital signal processor
real time
model checking
multi core architecture
texas instruments
data sets
functional verification
face verification
formal analysis
signature verification
verification method
concurrent systems
neural network
formal verification
layout design
case study
artificial intelligence
databases