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A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function.
Hideki Tanaka
Takashi Morie
Kazuyuki Aihara
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2009)
Keyphrases
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high speed
circuit design
analog vlsi
spiking neural networks
biologically inspired
delay insensitive
low power
low voltage
power consumption
spiking neurons
genetic algorithm
cmos technology
cerebellar model
artificial neural networks
biologically plausible
power dissipation