Login / Signup
A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS.
Yang You
Sudipto Chakraborty
Rui Wang
Jinghong Chen
Published in:
A-SSCC (2015)
Keyphrases
</>
decision feedback
duty cycle
circuit design
nm technology
high speed
cmos technology
power dissipation
random access memory
low power
multipath
error propagation
real time
power consumption
clock frequency
silicon on insulator
soft decision
intersymbol interference
low cost
low voltage
image sensor
end to end