Login / Signup
A dual-loop delay-locked loop using multiple voltage-controlled delay lines.
Yeon-Jae Jung
Seung-Wook Lee
Daeyun Shim
Wonchan Kim
Changhyun Kim
Soo-In Cho
Published in:
IEEE J. Solid State Circuits (2001)
Keyphrases
</>
data sets
critical path
real time
neural network
case study
three dimensional
optimal solution
line segments