A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters.
Rong LinPublished in: IPDPS (2003)
Keyphrases
- low power
- low cost
- signal processor
- vlsi architecture
- low power consumption
- hardware implementation
- power consumption
- high speed
- power reduction
- parallel architecture
- floating point
- single chip
- parallel computers
- systolic array
- distributed memory
- mixed signal
- cmos technology
- real time
- nm technology
- digital signal processing
- signal processing
- wireless transmission
- high power
- processing elements
- general purpose
- parallel implementation
- parallel processing
- vlsi circuits
- logic circuits
- linear algebra
- graphics processing units
- interconnection networks
- power saving
- hardware and software
- data flow
- embedded systems
- cmos image sensor
- gate array
- delay insensitive
- image sensor
- massively parallel
- parallel computing
- image processing algorithms
- shared memory
- error correction
- digital camera