Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.
Daniel G. SaabJacob A. AbrahamVivekananda M. VedulaPublished in: VLSI Design (2003)
Keyphrases
- bounded model checking
- formal verification
- model checking
- automated verification
- symbolic model checking
- satisfiability problem
- model checker
- sat solvers
- program slicing
- search algorithm
- temporal logic
- sat problem
- cooperative
- phase transition
- stochastic local search
- propositional satisfiability
- description language
- orders of magnitude
- multi agent systems
- artificial intelligence