A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder.
Yuan-Hsin LiaoGwo-Long LiTian-Sheuan ChangPublished in: IEEE Trans. Circuits Syst. Video Technol. (2012)
Keyphrases
- highly efficient
- low complexity
- vlsi architecture
- mpeg avc
- mode decision
- multithreading
- distributed video coding
- motion estimation
- video coding
- video encoder
- computational complexity
- vlsi implementation
- coding efficiency
- video codec
- bit plane
- low cost
- video coding standard
- real time
- video streaming
- motion compensated
- image compression
- decoding process
- image sequences