Reconfigurable buses with shift switches for fast final additions of parallel multipliers.
Rong LinPublished in: PDPTA (1997)
Keyphrases
- massively parallel
- parallel computing
- low cost
- parallel architectures
- processing elements
- artificial intelligence
- general purpose
- real time
- systolic array
- learning algorithm
- reconfigurable architecture
- shared memory
- parallel processing
- dynamic programming
- artificial neural networks
- search algorithm
- information retrieval
- real world