A low-power LDO circuit with a fast load regulation.
Young Jae JangSeong-Eun ChoByungsub KimJae-Yoon SimHong-June ParkPublished in: APCCAS (2016)
Keyphrases
- low power
- power reduction
- high speed
- power consumption
- cmos technology
- logic circuits
- low voltage
- low cost
- power dissipation
- gate array
- single chip
- high power
- delay insensitive
- wireless transmission
- vlsi circuits
- digital signal processing
- vlsi architecture
- image sensor
- low power consumption
- load balancing
- power saving
- energy efficiency
- nm technology