HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis.
Sajjad NouriJens RettkowskiDiana GöhringerJari NurmiPublished in: HEART (2017)
Keyphrases
- high level synthesis
- hw sw
- field programmable gate array
- hardware software partitioning
- hardware software co design
- embedded systems
- design space exploration
- hardware implementation
- parallel architecture
- hardware software
- design methodology
- high speed
- hardware design
- design space
- low cost
- computing systems
- parallel computing
- computer architecture
- image processing algorithms
- efficient implementation
- hardware and software
- signal processing
- real time
- design process
- parallel execution
- software engineering
- pattern recognition
- neural network