Formal Verification of Arithmetic RTL: Translating Verilog to C++ to ACL2.
David M. RussinoffPublished in: ACL2 (2020)
Keyphrases
- formal verification
- hardware description language
- model checking
- integrated circuit
- model checker
- automated verification
- bounded model checking
- model based diagnosis
- natural language learning
- programmable logic
- symbolic model checking
- program slicing
- arithmetic operations
- hardware designs
- hardware design
- source code
- functional verification
- field programmable gate array
- knowledge based systems