Parallel error correction algorithm in RNS VLSI digital circuits.
Elio D. Di ClaudioGianni OrlandiFrancesco PiazzaPublished in: ICASSP (1988)
Keyphrases
- digital circuits
- data flow
- processor array
- finite state machines
- error rate
- model based diagnosis
- signal processing
- error bounds
- vlsi circuits
- evolvable hardware
- distributed memory
- parallel computing
- functional decomposition
- mixed signal
- vlsi design
- circuit design
- computer architecture
- error analysis
- high speed
- databases
- decision diagrams
- shared memory
- np complete
- data model