A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS.
Ashkan Roshan-ZamirTakayuki IwaiYang-Hang FanAnkur KumarHae-Woong YangLee SledjeskiJohn HamiltonSoumya ChandramouliArlo AudeSamuel PalermoPublished in: CICC (2018)
Keyphrases
- data streams
- low overhead
- high speed
- decision feedback
- digital filters
- high reliability
- cmos technology
- load balancing
- silicon on insulator
- infinite impulse response
- low cost
- low power
- energy efficient
- finite impulse response
- data sets
- nm technology
- real time
- communication cost
- power consumption
- metal oxide semiconductor
- error propagation
- shared memory
- false alarm probability
- filter design
- filter bank
- active contours
- soft decision
- high precision
- low pass filter