Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs.
Koji InoueKoji KaiKazuaki J. MurakamiPublished in: HPCA (1999)
Keyphrases
- memory bandwidth
- level parallelism
- processing power
- cache misses
- floating point
- main memory
- memory access
- parallel programming
- processing units
- hardware and software
- commodity hardware
- limited resources
- parallel processing
- multi dimensional
- index structure
- data access
- high density
- query processing
- computing power
- parallel computing
- parallel algorithm
- database management systems
- cloud computing
- general purpose