Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect.
Melvin EzeOzcan OzturkVijaykrishnan NarayananPublished in: VLSI-SoC (2013)
Keyphrases
- high speed
- low power
- high density
- power consumption
- nm technology
- vlsi implementation
- mixed signal
- cmos technology
- power dissipation
- single chip
- management system
- real time
- cost effective
- low cost
- analog vlsi
- flip flops
- signal processor
- network architecture
- software architecture
- power management
- content addressable memory
- design considerations
- power system
- host computer
- cmos image sensor