An FPGA design of AES encryption circuit with 128-bit keys.

Hui Qin Tsutomu Sasao Yukihiro Iguchi

Published in: ACM Great Lakes Symposium on VLSI (2005)

Keyphrases

high speed
secret key
block cipher
real time
hardware design
power reduction
gate array
signal processing
circuit design
digital circuits
single chip
hardware architecture
design process
efficient implementation
hardware implementation
analog circuits