Run-time Cache Configuration for the LEON-3 Embedded Processor.
Bruno A. SilvaLucas Albers CuminatoVanderlei BonatoPedro C. DinizPublished in: SBCCI (2015)
Keyphrases
- embedded processors
- single chip
- dynamic random access memory
- parallel implementation
- memory subsystem
- low cost
- cache misses
- low power
- memory hierarchy
- processor core
- high speed
- optimal configuration
- multiprocessor systems
- operating system
- computer architecture
- embedded systems
- multithreading
- parallel processing
- database workloads
- central processing unit
- shared memory multiprocessors
- database systems