A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS.

Jaeyoung Kim Pinaki Mazumder

Published in: Integr. (2017)

Keyphrases

low power
ultra low power
power consumption
cmos technology
high speed
low cost
power reduction
nm technology
computationally efficient
neural network
data sets
objective function
support vector
delay insensitive
vlsi circuits