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A Tile-based Interconnect Model for FPGA Architecture Exploration.
Chengyu Hu
Qinghua Duan
Peng Lu
Wei Liu
Jian Wang
Jinmei Lai
Published in:
ACM Great Lakes Symposium on VLSI (2020)
Keyphrases
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high level
high speed
computational model
real time
management system
mathematical model
experimental data
image processing
multiscale
probabilistic model
probability distribution
theoretical analysis
parameter estimation
efficient implementation
selection mechanism