Dominance Testing via Model Checking.
Ganesh Ram SanthanamSamik BasuVasant G. HonavarPublished in: AAAI (2010)
Keyphrases
- model checking
- formal verification
- temporal logic
- automated verification
- temporal properties
- formal specification
- symbolic model checking
- model checker
- finite state machines
- finite state
- pspace complete
- reachability analysis
- partial order reduction
- epistemic logic
- software testing
- bounded model checking
- computation tree logic
- timed automata
- test cases
- reactive systems
- verification method
- concurrent systems
- process algebra
- transition systems
- test set
- alternating time temporal logic
- deterministic finite automaton
- artificial intelligence