VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM).

Siu Hong Loh You Hong Liew Jia-Jia Sim

Published in: ICCSCE (2022)

Keyphrases

vlsi design
design methodology
functional verification
formal verification
model checking
design process
formal methods
databases
real world
computer aided
user interface
case study
neural network
low cost
building blocks
application specific
low power consumption