Error Containment in the Time-Triggered System-On-a-Chip Architecture.

Roman Obermaisser Hermann Kopetz Christian El Salloum Bernhard Huber

Published in: IESS (2007)

Keyphrases

analog vlsi
vlsi implementation
real time
high speed
error rate
neural network
management system
low cost
host computer
single chip
signal processing
query evaluation
high density
design considerations