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High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic (XTL) interface.
Hideki Osaka
Toyohiko Komatsu
Susumu Hatano
Takeshi Wada
Published in:
Hot Interconnects (2001)
Keyphrases
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high speed
gigabit ethernet
high bandwidth
high density
low latency
main memory
end to end
low power
embedded dram
fiber optic
real time
frame rate
data acquisition
random access memory
memory subsystem