A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application.
Bong Hwa JeongJongwon LeeYin Jae LeeTae Jin KangJoo Hyeon LeeDuck Hwa HongJae Hoon KimEun Ryeong LeeMin Chang KimKyung Ha LeeSang Il ParkJong Ho SonSang Kwon LeeSeong Nyuh YooSung Mook KimTae Woo KwonJin-Hong AhnYong Tak KimPublished in: ISSCC (2009)
Keyphrases
- high speed
- low power
- mobile applications
- high power
- power consumption
- power dissipation
- single chip
- power reduction
- mobile devices
- cmos technology
- mobile phone
- low power consumption
- frame rate
- ultra low power
- user experience
- key distribution
- energy dissipation
- vlsi architecture
- real time
- mobile environments
- logic circuits
- image sensor
- digital signal processing
- low cost
- mobile users
- vlsi circuits
- mobile services
- low voltage
- power saving
- mixed signal
- context aware
- high density